Assembly and machine code
From assembly
From machine code
Current decoded instruction
——
32-bit binary
Hexadecimal
Interactive 32-bit instruction
Tick or untick the checkboxes to directly change the individual instruction bits.
Click any colored field below the bit checkboxes to expand it for a more detailed explanation.
Immediate formation / reconstruction
Select an immediate field above to inspect how its logical bits map into the 32-bit instruction.
Instruction-format encoding table
This mirrors the R/I/I*/S/B/U/J summary on the reference sheet: most register and opcode fields stay aligned, while S/B/J rearrange immediate bits.
Bit numbers run from 31 at the left to 0 at the right. The highlighted row follows the current word whenever its opcode identifies a supported format.
Immediate range checks: I/S signed immediates [−2048, 2047]; shift amounts [0, 31]; B offsets [−4096, 4094] and even; J offsets [−1,048,576, 1,048,574] and even; U-type immu is a 20-bit field [0, 0xFFFFF].
RV32I reference sheet — supported class subset
RISC-V RV32I instruction set subset based on the University of California, Berkeley CS 61C class (https://cs61c.org/). Simplified for instructional purposes.