Systolic array cycle simulator

See how a systolic array performs a matrix computation cycle by cycle.

Conceptualized by Adelson Chua.

Dataflow
PE architecture
Matrix Configuration Click to collapse feature / A filter / B product accumulator output shift
Cycle number
0
Feed cycle t
—
Expected C = A × B

Timing table for input matrices

During feed cycle t: row r carries A[r][t-r] for r ≤ t < r+K; column c carries B[t-c][c] for c ≤ t < c+K. The highlighted row below is the currently prepared feed cycle.