Theme: ☀️ Light
Topology:
FF1 -> Logic -> FF2
FF Params:
Shared FF parameters
Advanced: Off
SETUP
HOLD
Circuit Topology 2 FF Path
Clock Period
T (period) 10.0 ns
Flip-Flop Parameters
tC-Q 1.0 ns
tsetup 1.0 ns
thold 0.5 ns
FF2 — Destination FF2
tC-Q (FF2) 1.0 ns
tsetup (FF2) 1.0 ns
thold (FF2) 0.5 ns
FF3 Destination FF3
tsetup (FF3) 1.0 ns
thold (FF3) 0.5 ns
Combinational Logic Delay
tLmin 2.0 ns
tLmax 5.0 ns
tLmin < tLmax enforced automatically
Combinational Logic Delay 2
tLmin 2.0 ns
tLmax 5.0 ns
tLmin < tLmax enforced automatically
Clock Non-Idealities
tskew magnitude 0.0 ns
CLK2 direction:
CLK1 = FF1 clock  ·  CLK2 = FF2 clock ± tskew
tjitter 0.0 ns
±tjitter uncertainty shown on clock edges
Timing Waveform
CLK
Q
Logic / D rows
Unstable (tLmin…Lmax)
Setup window
Hold window
CLK2 (skewed)
Jitter ±tj
Setup Time Constraint
T ≥ tC-Q + tLmax + tsetup
≥
SETUP TIMING MET
Hold Time Constraint
thold ≤ tC-Q + tLmin
≤
HOLD TIMING MET
Maximum Operating Frequency
fmax = T = slack =