Press Step to process the highlighted access.
Virtual to Physical address mapping
Translation changes the page number and keeps the offset.
Cache & TLB
When V = 0, entry values are ignored. Initialization restarts the series.
Main memory
Physical pages contain data and the page table.
Purple: page-table bytes. Gold: current transfer.
Access history
Newest completed access first.
| # | Op | Virtual | Physical | TLB | Cache | Result / value | Page traffic |
|---|
Model notes
The PTBR points to the page table in RAM. Each PTE starts with Valid, Dirty, and Write protect at its three most significant bits. The physical page number (PPN) occupies bits 3–0; the intervening bits are reserved. PTE size is selectable.
A TLB miss reads the PTE. With caches disabled, each request walks the table and accesses RAM directly. A page fault can load a page from secondary storage and retry.
Write-back stores modify the cache and set its dirty bit. Dirty blocks return to RAM before replacement or page-out. In this simulator, the PTE dirty bit marks RAM data modified since its last disk copy. Cached stores leave it unchanged; cache write-back sets it. Page replacement flushes dirty cache blocks before checking the PTE dirty bit, then saves a dirty RAM page to disk. Page-out clears that bit. This Dirty-bit timing is a teaching abstraction: real MMUs such as RISC-V mark the page dirty on a store, even while its data remains in a write-back cache. Loads return unsigned data; register sign extension and cycle timing are not modeled. Real page tables are often multilevel.
Changes and initialization restart the series. Reset keeps the current mappings. Undo restores the previous access; Tutorial Back restores an earlier stage.