Digital Design Group · UP EEEi
Digital Design Resources
Course materials, interactive simulation tools, and open-source hardware from the Digital Design Group at the University of the Philippines Diliman.
Interactive Tools
Browser-based tools — no installation needed
Semiconductor fundamentals
Diode Characterization
Compare PN, Schottky, and Zener diodes through interactive current-voltage curves, depletion regions, band diagrams, and capacitance.
BJT Characterization
Adjust NPN and PNP transistor bias conditions and explore characteristic curves, junction currents, and animated carrier transport.
MOS Transistor Fundamentals
Digital Design Fundamentals
kmap-gamEEE
Practice Karnaugh map simplification through interactive puzzles with immediate feedback.
FSMsimulatEEE
Draw and simulate finite state machines directly in your browser. Fully client-side — no server required.
Algorithmic State Machine Simulator
Simulate ASM charts with interactive execution and visualization of state transitions, conditions, and outputs.
Timing Simulator
Need to confirm what you know about sequential circuits and timing constraints? Visualize and simulate the definitions of sequential timing here.
Computer Architecture
RIPES
Explore RISC-V processor architectures and visualize instruction execution.
RV32I Encoding Simulator
Assemble and inspect RISC-V RV32I instructions, including their encoded fields, binary representation, and hexadecimal output.
Cache Memory Simulator
Configure a cache and simulate memory accesses to explore address partitioning, cache contents, and access history.
Virtual Memory Simulator
Explore virtual-to-physical address translation, page tables, TLBs, and page faults with interactive memory accesses.
Hardware for Machine Learning
Course Materials
Open educational resources for digital design
Course Material · 6 Modules
Verilog Crash Course
A structured introduction to Verilog HDL covering combinational logic, sequential circuits, finite state machines, verification techniques, and coding best practices. Originally deployed on UVLe.
View Course →
Hardware Resources
RTL we've built and open-sourced
Open Source · GitLab
AllenCore
A pipelined RV32IMC processor implementing the RISC-V base integer ISA with multiply (M) and compressed instruction (C) extensions. Targets the Artix A7-200T.
Open Source · GitHub
ADEL Processor
A minimal processor with a simple custom ISA designed to teach students processor architecture fundamentals. DRC,LVS clean on the SkyWater 130nm open PDK.